Cappel's Experimental 1 KHz Synchronous Detector
Overview
This circuit employs a synchronous demodulator to separate a 1 KHz signal from noise and measures the amplitude of the 1 kHz signals once a second at about 60 microvolts per count then sends the measurements via an RS-232 interface for further processing or display. An LED on the board also lights when the measured signal exceeds a preset threshold.
This experiment was started when I took an interest in receiving ELF wireless signals. It also has applictions in optics and high frequency RF, or for that matter, any place one needs to measure a tiny signal, of which the frequency and phase are known, in the presence of noise.
With the addition of a preamplifier based on the LM324, the sensitivity of this circuit was easily extended to a sensitivity to 160 nanovolts per count. That an LM324 is used with little in the way of noise on the output testifies to the value of using this kind of detector.
How it works
The detector is a multiplier fillowed by an integrator.
A single slope analog to digital conversion process measures the
detected signal with 7 bit resolution.
There are several sophisticated references on the web that describe how synchronous detectors work, so here I will only give a light overview and go into some specifics of this implementation.
The idea is to multiply the input signal by the output of a local oscillator that is synchronized with the expected signal, and integrate the result. Imagine a square wave being fed into the signal input of the multiplier and a synchronized square wave being fed into the local oscillator input of the multiplier. If the local oscillator is synchronized such that they are perfectly matched in phase, then the output of the multiplier will be positive when the incoming signal and the local oscillator are positive and the output will also be positive when the inputs are negative (negative x negative = positive) this is actually a full wave rectifier when both signals are synchronized and in the proper phase with one another.
In theory, signals at the proper frequency are presented as DC to the integrator and all other frequencies average out to zero. In practice, this circuituses square waves to perform the modulation, so it is susceptible to odd harmonics of the sampling frequency, so it is sensitive to 3 kHz, 5 kHz, 7 kHz..., so an analog filter ahead of the detector can be useful if it is important to reject these frequencies.
The circuit
All the analog circuits are biased to operate around a 1.8v reference.
The incoming signal is buffered by U2A (there is on U1 in this schematic as U1 was moved to a separate preamp assembly), which provides a noniverted signal to the integrator when U3A is switched on. U2B inverts the buffered signal from U2A and provides an inverted version of the signal to the integrator when U3B is switched on. To increase the charging rate, either decrease the 100k resistor on the input of U2C or decrease the .047 uf integrating capacitor.
On the output of the integrator, input noise tends to average out.
The signals fed into the integrator charge the .047 uf capacitor in the integrator. After 999 cycles of the 1 kHz sampling signal, U3C is turned on and the capacitor is discharged with a constant current (1.8V/7.5K = 240 microamps), producing a linear positive-going ramp at 5,106 volts/second on the output of U2C. While the output of U2 is ramping up toward the 1.8 volt reference, the AT90S2313 sits in a loop, incrementing a counter every 1.25 microseconds, until the comparitor on the AT90S2313 changes state, indicating that the ramp on U2C has reached the 1.8 volt reference voltage. The maximum count for this measurement is 127 to limit the time spent in the measurement to less than the 250 microsecond interrupt interval. Thus, a 7 bit measurement is made in 160 microseconds or less, and is completed within a single 250 microsecond interrupt interval.
The rate of discharge of the integrating capacitor during the measurement phase is set by the current into the node, 1.8 volts/7.5 k =240 microamps, divided by the .047 uf capacitance, which gives a 5100 volt/second voltage ramp. The A/D conversion sensitivity is therefore 1.25 us/count X 5100 volts/second = 6.375 millivolts per count.
After the count is completed, which occurs when the pseudo 7 bit counter overflows or the ramp reaches the 1.8 volt reference, U3C is switched off and U3D is switched on to clamp the of the integrator to the 1.8 volt reference and to make sure the capacitor is discharged to a consistent state for 1 millisecond before starting signal measurement again,
The entire measurement cycle takes 999 milliseconds for integration + 1 millisecond to clamp the capacitor to zero, for a total of 1 second per measurement.
The gian of the integrator is ( ( Peak input Voltage/ 100 k Ohm) X 0.999 seconds ) )/ .047 microfarads = 212.5 volts out/volt in. The sensitivity of the detector is therefore 6.375 mv/212.5 = 30 microvolts peak per count, or since peak-to-peak = 2 x peak, 60 microvolts peak-to-peak per count.
After the measurement is completed, the measured value is formatted into BCD and sent via the UART at 9600 baud, two stop bits, no parity. The transmission of the data does not occur during interrupt time.
An LED is turned on by the microcontroller during the integration and measurement cycle following a measurement in which the measured value exceeded 64 decimal.
The sensitivity of this particular hardware assembly is 5 millivolts/(87 counts - 18 counts) = 72.4 microvolts per count. This number is reasonable close to the calculated sensitivitiy of 60 microvolts per count. The error might be becasue the input signal was larger than I thought.
This sensitivity, 72 microvolts per count, is for square waves. The sensitivity for sine waves will be 63.7% of the sensitivity for square waves. Also note that if the incoming signal is not perfectly phased with respect to the sampling signal, the amplifude will be reduce.
The circuit can be made more sensitive by decreasing the 100k resistor connected to pin 9 of U2C, by reducing the ,047 uf integrating capacitor, or increasing the integration time, which is currently set to 999 cycles. Reducing the resistor or capacitor will reduce the circuit's ability to reject interfering signals at frequenices not at the sampling frequency. Increasing the integration time will raise the senstitivity without affecting the ability to reject interfering signals, but the offset control becomes very touchy with integration times of more than a few thousand cycles.
Link: http://cappels.org/dproj/syncdet/syncdet.html
Overview
This circuit employs a synchronous demodulator to separate a 1 KHz signal from noise and measures the amplitude of the 1 kHz signals once a second at about 60 microvolts per count then sends the measurements via an RS-232 interface for further processing or display. An LED on the board also lights when the measured signal exceeds a preset threshold.
This experiment was started when I took an interest in receiving ELF wireless signals. It also has applictions in optics and high frequency RF, or for that matter, any place one needs to measure a tiny signal, of which the frequency and phase are known, in the presence of noise.
With the addition of a preamplifier based on the LM324, the sensitivity of this circuit was easily extended to a sensitivity to 160 nanovolts per count. That an LM324 is used with little in the way of noise on the output testifies to the value of using this kind of detector.
How it works
The detector is a multiplier fillowed by an integrator.
A single slope analog to digital conversion process measures the
detected signal with 7 bit resolution.
There are several sophisticated references on the web that describe how synchronous detectors work, so here I will only give a light overview and go into some specifics of this implementation.
The idea is to multiply the input signal by the output of a local oscillator that is synchronized with the expected signal, and integrate the result. Imagine a square wave being fed into the signal input of the multiplier and a synchronized square wave being fed into the local oscillator input of the multiplier. If the local oscillator is synchronized such that they are perfectly matched in phase, then the output of the multiplier will be positive when the incoming signal and the local oscillator are positive and the output will also be positive when the inputs are negative (negative x negative = positive) this is actually a full wave rectifier when both signals are synchronized and in the proper phase with one another.
In theory, signals at the proper frequency are presented as DC to the integrator and all other frequencies average out to zero. In practice, this circuituses square waves to perform the modulation, so it is susceptible to odd harmonics of the sampling frequency, so it is sensitive to 3 kHz, 5 kHz, 7 kHz..., so an analog filter ahead of the detector can be useful if it is important to reject these frequencies.
The circuit
All the analog circuits are biased to operate around a 1.8v reference.
The incoming signal is buffered by U2A (there is on U1 in this schematic as U1 was moved to a separate preamp assembly), which provides a noniverted signal to the integrator when U3A is switched on. U2B inverts the buffered signal from U2A and provides an inverted version of the signal to the integrator when U3B is switched on. To increase the charging rate, either decrease the 100k resistor on the input of U2C or decrease the .047 uf integrating capacitor.
On the output of the integrator, input noise tends to average out.
The signals fed into the integrator charge the .047 uf capacitor in the integrator. After 999 cycles of the 1 kHz sampling signal, U3C is turned on and the capacitor is discharged with a constant current (1.8V/7.5K = 240 microamps), producing a linear positive-going ramp at 5,106 volts/second on the output of U2C. While the output of U2 is ramping up toward the 1.8 volt reference, the AT90S2313 sits in a loop, incrementing a counter every 1.25 microseconds, until the comparitor on the AT90S2313 changes state, indicating that the ramp on U2C has reached the 1.8 volt reference voltage. The maximum count for this measurement is 127 to limit the time spent in the measurement to less than the 250 microsecond interrupt interval. Thus, a 7 bit measurement is made in 160 microseconds or less, and is completed within a single 250 microsecond interrupt interval.
The rate of discharge of the integrating capacitor during the measurement phase is set by the current into the node, 1.8 volts/7.5 k =240 microamps, divided by the .047 uf capacitance, which gives a 5100 volt/second voltage ramp. The A/D conversion sensitivity is therefore 1.25 us/count X 5100 volts/second = 6.375 millivolts per count.
After the count is completed, which occurs when the pseudo 7 bit counter overflows or the ramp reaches the 1.8 volt reference, U3C is switched off and U3D is switched on to clamp the of the integrator to the 1.8 volt reference and to make sure the capacitor is discharged to a consistent state for 1 millisecond before starting signal measurement again,
The entire measurement cycle takes 999 milliseconds for integration + 1 millisecond to clamp the capacitor to zero, for a total of 1 second per measurement.
The gian of the integrator is ( ( Peak input Voltage/ 100 k Ohm) X 0.999 seconds ) )/ .047 microfarads = 212.5 volts out/volt in. The sensitivity of the detector is therefore 6.375 mv/212.5 = 30 microvolts peak per count, or since peak-to-peak = 2 x peak, 60 microvolts peak-to-peak per count.
After the measurement is completed, the measured value is formatted into BCD and sent via the UART at 9600 baud, two stop bits, no parity. The transmission of the data does not occur during interrupt time.
An LED is turned on by the microcontroller during the integration and measurement cycle following a measurement in which the measured value exceeded 64 decimal.
The sensitivity of this particular hardware assembly is 5 millivolts/(87 counts - 18 counts) = 72.4 microvolts per count. This number is reasonable close to the calculated sensitivitiy of 60 microvolts per count. The error might be becasue the input signal was larger than I thought.
This sensitivity, 72 microvolts per count, is for square waves. The sensitivity for sine waves will be 63.7% of the sensitivity for square waves. Also note that if the incoming signal is not perfectly phased with respect to the sampling signal, the amplifude will be reduce.
The circuit can be made more sensitive by decreasing the 100k resistor connected to pin 9 of U2C, by reducing the ,047 uf integrating capacitor, or increasing the integration time, which is currently set to 999 cycles. Reducing the resistor or capacitor will reduce the circuit's ability to reject interfering signals at frequenices not at the sampling frequency. Increasing the integration time will raise the senstitivity without affecting the ability to reject interfering signals, but the offset control becomes very touchy with integration times of more than a few thousand cycles.
Link: http://cappels.org/dproj/syncdet/syncdet.html