3 Channel, 8 bit EEPROM DAC with DS interface
•Low power
•EEPROM memory for autonomous operation, 16 bytes available for general purpose use.
•Low cost
This device provides three channels of 8 bit pulse-width modulation. Output pulse duty cycle ranges from 0 to 255/256 in 255 steps. DACs may be loaded by the DS interface. DAC values may also be copied into the on-chip EERPOM and then automatically be loaded into the DACs when power is applies, making it useful for automatic set up of circuits that do not contain microcontrollers. This replaces more expensive EEPROM DACs and EEPROM pots in many applications, owing to its use of a small area high volume integrated circuit microcontroller. Additionally, one page of 16 bytes of on-chip EEPROM storage is accessible via the DS interface.
Pinouts of the DAC. Avoid long parallel traces or flat ribbon cable runs with the PWM0 and Attention line signals in parallel in such a way that the PWM0 signal couples heavily into the Attention line as this signal could make the interface hang up .
When programming the chip it is recommended elect internal oscillator and set the brownout detector to the high voltage consistent with your application.
Hardware considerations
With the values for the RC (resistor-capacitor) filters given on the schematic above, the worst case ripple will be about 1/2 lsb at 5V. Lower power supply voltages casue the ATtiny12's osciallator frequency to dorp, thus to maintain 1/2 lsb ripple, it would be necessary to increase the resistors or the capcaitors in the output filter.
If during reset initialization, the EEPROM checksum is found to be correct, the DAC values stored in EEPROM will be loaded into the DACs. As such, the DS interface pins can be permanently tied to ground if the situation calls for it. Similarly, if the reset input is not used, the 100k resistor may be omitted and pin 1 tied directly to VCC. If the reset input is tied directly to VCC check the final assembly language code carefully to make sure that DDRB bit 5 is never set as an output and PB5 is never driven low because port B bit 5 is an alternative function of pin 1.
This DS slave device does not have any internal pull-ups. This chip uses the same PWM generation method as the 8 channel 8 bit DAC. See this page for details of operation.
It should be noted that the VCC of the PWM DAC needs to be close to the VCC of the host. Check the device's respective data sheets for details.
The DS DAC is composed of a DS interface followed by an Incoming Data Register and an Instruction Interpreter. The instruction interpreter moves to and from the register file and the EEPROM and controls the DAC control. Instructions provide for reading from and writing the register set and the EEPROM.
Using the DS interface, DAC values are written to registers 0, 1, and 2 to control DAC 0, 1, and 2, respectively. The DAC control blocks creates a bit-reversed image for use by the PWM routines and places them in registers 4,5, and 6. A command allows the register set and a checksum to be written to a dedicated section of the EEPROM. As part of the rest initialization routine, the EEPROM data are checked against the checksum and if the checksum is valid, registers 0,1, and 2 will be loaded from the EEPROM and DAC operation commenced using the stored data.
Sixteen bytes of on-chip EEPROM are accessible directly and useable at the discretion of the programmer. The EEPROM is written every time an instruction to write to the EEPROM (instruction $4X) is interpreted -since the manufacturer only guarantees the EEPROM to work for a limited number of erase-write cycles (100,000 at the time of this writing), routines that frequently write to the EEPROM should be avoided. Note that when the EEPROM is written, the stored checksum becomes invalid and the automatic loading of the DAC values after reset will not work again until the command to write a new checksum to the EEPROM (command $70) is interpreted.
REGISTER FUNCTION0........................Store DAC0 input value here1........................Store DAC1 input value here2........................Store DAC2 input value here3........................Not used. May be used for a fourth channel in the future.4........................DAC0 working storage (bit-reversed pattern of register 0)5........................DAC1 working storage (bit-reversed pattern of register 1)6........................DAC2 working storage (bit-reversed pattern of register 2)7........................Not used. May be used for a fourth channel in the future.8........................Not used by DAC and is available for use9........................Not used by DAC and is available for useA........................Not used by DAC and is available for useB........................Not used by DAC and is available for useC........................Not used by DAC and is available for useD........................Not used by DAC and is available for useE........................Used by DAC for internal purposes. Best not to modify this oneF........................Used by DAC for internal purposes. Best not to modify this one
Instruction Set
$1R store data in register set
$2R read data from register set
$4A store to EEPROM at address
$5A read data from EEPROM at address
$60 write PWM data registers to and checksum EEPROM
$70 write EEPROM checksum to EEPROM
$80 read revision level of firmware
$90 write EEPROM data to PWM registers
The use of R and A above indicate register numbers and EEPROM addresses, respectively. F or example, command $1C would write the contents of the Incoming Data Register to register $C in the register set and command $2C would read the contents of that register back to the host. Similarly commands $48 and $58 would write and read EEPROM location 8 in devices that have EEPROM.
Detailed Description of Instruction Set
$1R store data in register set
Store data in one of the 16 registers $0..$F. For example, register 2 may be written with the data previously sent to the Incoming Data Register. by writing the command $12.
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$2R read data from register set
Read data from register indicated. For example to read the value of the data in register 2, write the command $22.
$4A store to EEPROM at address
Store data in one of the 16 EEPROM locations, $0..$F. For example EEPROM location 2 may be written with the data previously sent to the Incoming Data Register by writing the command $42. Writing to the EEPROM with this command will void any previously stored checksum and a write checksum to EEPROM command (command $70) must be executed before DAC values stored in EEPROM will be automatically used during reset initialization.
This command writes directly to the EEPROM and the limited number of erase-write cycles needs to be paid attention to. See the manufacturer's data sheet for more information.
$5A read data from EEPROM at address
Read data from EEPROM at address indicated. For example to read the value of the data in at EEPROM address 2, write the command $52.
$60 write PWM data registers and checksum to EEPROM
Writes registers 0, 1, and 2 along with a checksum to the EEPROM.
$70 write EEPROM checksum to EEPROM
Calculated EEPROM checksum and writes it to the EEPROM.
$80 read revision level of firmware
Causes the DS DAC to send two data bytes. The first byte is the version of the DAC and the second byte is the minor revision level.
$90 write EEPROM data to PWM registers
This command is useful for restoring previously stored values after modification. For example, a default DAC value can be stored using the write PWM data registers and checksum to the EEPROM command (command $60), and the DAC values then replaced. Unless the write PWM data registers and checksum to EEPROM command (command $60) is issued after the modification, using the write EEPROM to PWM data registers (this command, command $90) will restore the default DAC values, as will resetting the chip.
Link to Site: http://cappels.org/dproj/DSDACpage/dsdac.htm
•Low power
•EEPROM memory for autonomous operation, 16 bytes available for general purpose use.
•Low cost
This device provides three channels of 8 bit pulse-width modulation. Output pulse duty cycle ranges from 0 to 255/256 in 255 steps. DACs may be loaded by the DS interface. DAC values may also be copied into the on-chip EERPOM and then automatically be loaded into the DACs when power is applies, making it useful for automatic set up of circuits that do not contain microcontrollers. This replaces more expensive EEPROM DACs and EEPROM pots in many applications, owing to its use of a small area high volume integrated circuit microcontroller. Additionally, one page of 16 bytes of on-chip EEPROM storage is accessible via the DS interface.
Pinouts of the DAC. Avoid long parallel traces or flat ribbon cable runs with the PWM0 and Attention line signals in parallel in such a way that the PWM0 signal couples heavily into the Attention line as this signal could make the interface hang up .
When programming the chip it is recommended elect internal oscillator and set the brownout detector to the high voltage consistent with your application.
Hardware considerations
With the values for the RC (resistor-capacitor) filters given on the schematic above, the worst case ripple will be about 1/2 lsb at 5V. Lower power supply voltages casue the ATtiny12's osciallator frequency to dorp, thus to maintain 1/2 lsb ripple, it would be necessary to increase the resistors or the capcaitors in the output filter.
If during reset initialization, the EEPROM checksum is found to be correct, the DAC values stored in EEPROM will be loaded into the DACs. As such, the DS interface pins can be permanently tied to ground if the situation calls for it. Similarly, if the reset input is not used, the 100k resistor may be omitted and pin 1 tied directly to VCC. If the reset input is tied directly to VCC check the final assembly language code carefully to make sure that DDRB bit 5 is never set as an output and PB5 is never driven low because port B bit 5 is an alternative function of pin 1.
This DS slave device does not have any internal pull-ups. This chip uses the same PWM generation method as the 8 channel 8 bit DAC. See this page for details of operation.
It should be noted that the VCC of the PWM DAC needs to be close to the VCC of the host. Check the device's respective data sheets for details.
The DS DAC is composed of a DS interface followed by an Incoming Data Register and an Instruction Interpreter. The instruction interpreter moves to and from the register file and the EEPROM and controls the DAC control. Instructions provide for reading from and writing the register set and the EEPROM.
Using the DS interface, DAC values are written to registers 0, 1, and 2 to control DAC 0, 1, and 2, respectively. The DAC control blocks creates a bit-reversed image for use by the PWM routines and places them in registers 4,5, and 6. A command allows the register set and a checksum to be written to a dedicated section of the EEPROM. As part of the rest initialization routine, the EEPROM data are checked against the checksum and if the checksum is valid, registers 0,1, and 2 will be loaded from the EEPROM and DAC operation commenced using the stored data.
Sixteen bytes of on-chip EEPROM are accessible directly and useable at the discretion of the programmer. The EEPROM is written every time an instruction to write to the EEPROM (instruction $4X) is interpreted -since the manufacturer only guarantees the EEPROM to work for a limited number of erase-write cycles (100,000 at the time of this writing), routines that frequently write to the EEPROM should be avoided. Note that when the EEPROM is written, the stored checksum becomes invalid and the automatic loading of the DAC values after reset will not work again until the command to write a new checksum to the EEPROM (command $70) is interpreted.
REGISTER FUNCTION0........................Store DAC0 input value here1........................Store DAC1 input value here2........................Store DAC2 input value here3........................Not used. May be used for a fourth channel in the future.4........................DAC0 working storage (bit-reversed pattern of register 0)5........................DAC1 working storage (bit-reversed pattern of register 1)6........................DAC2 working storage (bit-reversed pattern of register 2)7........................Not used. May be used for a fourth channel in the future.8........................Not used by DAC and is available for use9........................Not used by DAC and is available for useA........................Not used by DAC and is available for useB........................Not used by DAC and is available for useC........................Not used by DAC and is available for useD........................Not used by DAC and is available for useE........................Used by DAC for internal purposes. Best not to modify this oneF........................Used by DAC for internal purposes. Best not to modify this one
Instruction Set
$1R store data in register set
$2R read data from register set
$4A store to EEPROM at address
$5A read data from EEPROM at address
$60 write PWM data registers to and checksum EEPROM
$70 write EEPROM checksum to EEPROM
$80 read revision level of firmware
$90 write EEPROM data to PWM registers
The use of R and A above indicate register numbers and EEPROM addresses, respectively. F or example, command $1C would write the contents of the Incoming Data Register to register $C in the register set and command $2C would read the contents of that register back to the host. Similarly commands $48 and $58 would write and read EEPROM location 8 in devices that have EEPROM.
Detailed Description of Instruction Set
$1R store data in register set
Store data in one of the 16 registers $0..$F. For example, register 2 may be written with the data previously sent to the Incoming Data Register. by writing the command $12.
|
$2R read data from register set
Read data from register indicated. For example to read the value of the data in register 2, write the command $22.
$4A store to EEPROM at address
Store data in one of the 16 EEPROM locations, $0..$F. For example EEPROM location 2 may be written with the data previously sent to the Incoming Data Register by writing the command $42. Writing to the EEPROM with this command will void any previously stored checksum and a write checksum to EEPROM command (command $70) must be executed before DAC values stored in EEPROM will be automatically used during reset initialization.
This command writes directly to the EEPROM and the limited number of erase-write cycles needs to be paid attention to. See the manufacturer's data sheet for more information.
$5A read data from EEPROM at address
Read data from EEPROM at address indicated. For example to read the value of the data in at EEPROM address 2, write the command $52.
$60 write PWM data registers and checksum to EEPROM
Writes registers 0, 1, and 2 along with a checksum to the EEPROM.
$70 write EEPROM checksum to EEPROM
Calculated EEPROM checksum and writes it to the EEPROM.
$80 read revision level of firmware
Causes the DS DAC to send two data bytes. The first byte is the version of the DAC and the second byte is the minor revision level.
$90 write EEPROM data to PWM registers
This command is useful for restoring previously stored values after modification. For example, a default DAC value can be stored using the write PWM data registers and checksum to the EEPROM command (command $60), and the DAC values then replaced. Unless the write PWM data registers and checksum to EEPROM command (command $60) is issued after the modification, using the write EEPROM to PWM data registers (this command, command $90) will restore the default DAC values, as will resetting the chip.
Link to Site: http://cappels.org/dproj/DSDACpage/dsdac.htm