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;************************************************************* ;**** Deklarationsteil fuer die Hardware der Prozessoren ***** ;************************************************************* .equ ACSR = $08 ;Analog Comparator Control ;and Status Register .equ UBRR = $09 ;UART Baud Rate Register .equ UCR = $0a ;UART Control Register .equ USR = $0b ;UART Status Register .equ UDR = $0c ;UART Data Register .equ SPCR = $0d ;SPI Control Register .equ SPSR = $0e ;SPI Status Register .equ SPDR = $0f ;SPI Data Register .equ PIND = $10 ;Input Pins, Port D .equ DDRD = $11 ;Data direction Register, Port D .equ PORTD = $12 ;Data Register, Port D .equ PINC = $13 ;Input Pins, Port C .equ DDRC = $14 ;Data Direction Register, Port C .equ PORTC = $15 ;Data Register, Port C .equ PINB = $16 ;Input Pins, Port B .equ DDRB = $17 ;Data Direction Register, Port B .equ PORTB = $18 ;Data Register, Port B .equ PINA = $19 ;Input Pins, Port A .equ DDRA = $1a ;Data Direction Register, Port A .equ PORTA = $1b ;Data Register, Port A .equ EECR = $1c ;EEPROM Control Register .equ EEDR = $1d ;EEPROM Data Register .equ EEAR = $1e ;EEPROM Adress Register in 1200 .equ EEARL = $1e ;EEPROM Adress Register Low Byte .equ EEARH = $1f ;EEPROM Adress Register High Byte .equ WDTCR = $21 ;Watchdog Timer Control Register .equ ICR1L = $24 ;Timer/Counter 1 Input ;Capture Register Low .equ ICR1H = $25 ;Timer/Counter 1 Input ;Capture Register High .equ OCR1BL = $28 ;Timer/Counter 1 Output ;Compare Register B Low .equ OCR1BH = $29 ;Timer/Counter 1 Output ;Compare Register B High .equ OCR1AL = $2a ;Timer/Counter 1 Output ;Compare Register A Low .equ OCR1AH = $2b ;Timer/Counter 1 Output ;Compare Register A High .equ TCNT1L = $2c ;Timer/Counter 1 Daten Low .equ TCNT1H = $2d ;Timer/Counter 1 Daten High .equ TCCR1B = $2e ;Timer/Counter 1 Control ;Register B .equ TCCR1A = $2f ;Timer/Counter 1 Control ;Register A .equ TCNT0 = $32 ;Timer/Counter 0 Data .equ TCCR0 = $33 ;Timer/Counter 0 Control ;Register .equ MCUSR = $34 ;MCU Status Register .equ MCUCR = $35 ;MCU Control Register .equ TIFR = $38 ;Timer/Counter Interrupt ;Flag Register .equ TIMSK = $39 ;Timer/Counter Interrupt ;Mask Register .equ GIFR = $3a ;General Interrupt Flag Register .equ GIMSK = $3b ;General Interrupt Mask Register .equ SPL = $3d ;Stack Pointer Low .equ SPH = $3e ;Stack Pointer High .equ SREG = $3f ;Status Register .def XL = r26 .def XH = r27 .def YL = r28 .def YH = r29 .def ZL = r30 ;Lowbyte Z-Register .def ZH = r31 ;Highbyte Z-Register ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; avrkreis.asm ; Burkhard John ; 6.4.1999 .include "register.asm" ; AT90S1200 .equ RAMTOP = $1d ;letzte RAM-Adresse, R30 und R31 ;sind das Z-Register .equ FLASHTOP = $1ff ;letzte Flash-Adresse ;----------- ;Systemkonstanten .equ pausenlaenge = 256 .equ anzahltakte = 255 ;****************************************************************** ; Varaiblendeklaration .def dummy = r16 .def dummyh = r17 .def xdummy = r18 .def xdummyh = r19 .def zaehler = r20 .def uebergabe = r21 .def uebergabeh = r22 ;****************************************************************** ; Hier beginnt das Programm ;****************************************************************** .cseg .org 0 ;Startadresse des Programms systemstart: ;Interruptvektoren ; AT90S1200 rjmp start ;Systemstart nach Reset rjmp externint0 ;Externer Interrupt 0 rjmp timer0int ;Timer0 Interrupt rjmp ana_comp ;Analog Comparator ;------------- start: ;Alle Ports auf Ausgabe ldi uebergabe,$ff out DDRB,uebergabe out DDRD,uebergabe main: immerrund: ldi zaehler,anzahltakte ldi dummy,-2 ldi dummyh,-1 immerrund1: rcall pause out PORTB,dummy out PORTD,dummyh sbrc dummyh,6 rjmp irbitist1 clc rjmp irweiter irbitist1: sec irweiter: rol dummy rol dummyh dec zaehler brne immerrund1 immerrundr: ldi zaehler,anzahltakte immerrundr1: rcall pause out PORTB,dummy out PORTD,dummyh ror dummyh ror dummy brcs bitist1r cbr dummyh,$40 rjmp weiterr bitist1r: sbr dummyh,$40 weiterr: dec zaehler brne immerrundr1 dimmerrund: ldi zaehler,anzahltakte ldi dummy,-2 ldi dummyh,-2 dimmerrund1: rcall pause out PORTB,dummy out PORTD,dummyh sbrc dummyh,6 rjmp dirbitist1 clc rjmp dirweiter dirbitist1: sec dirweiter: rol dummy rol dummyh dec zaehler brne dimmerrund1 dimmerrundr: ldi zaehler,anzahltakte dimmerrundr1: rcall pause out PORTB,dummy out PORTD,dummyh ror dummyh ror dummy brcs dbitist1r cbr dummyh,$40 rjmp dweiterr dbitist1r: sbr dummyh,$40 dweiterr: dec zaehler brne dimmerrundr1 ximmerrund: ldi zaehler,anzahltakte ldi dummy,-2 ldi dummyh,-1 ldi xdummy,-2 ldi xdummyh,-2 ximmerrund1: rcall pause mov uebergabe,dummy and uebergabe,xdummy mov uebergabeh,dummyh and uebergabeh,xdummyh out PORTB,uebergabe out PORTD,uebergabeh sbrc dummyh,6 rjmp xirbitist1 clc rjmp xirweiter xirbitist1: sec xirweiter: rol dummy rol dummyh ror xdummyh ror xdummy brcs xdbitist1r cbr xdummyh,$40 rjmp xdweiterr xdbitist1r: sbr xdummyh,$40 xdweiterr: dec zaehler brne ximmerrund1 rjmp main ;***************************************************************** pause: clr uebergabe ldi uebergabeh,pausenlaenge pause1: dec uebergabe brne pause1 dec uebergabeh brne pause1 ret ;***************************************************************** ;Interrupts kuzrschliessen externint0: reti timer0int: reti ana_comp: reti |