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;Date 05/27/2004 ;Name Stephen L. Nuttall ;Hardware platform AVR Butterfly/STK500 ;Software platform Assembler/Studio 4 ;Processor mega169 ;Clock default internal RC oscillator/32KHz crystal ; ;The purpose of this code is for me to learn how to write characters ;to the AVR Butterfly LCD display. I will just try to display NOP. ;(I am not spoofing the AVR "nop" instruction, these are the initials we ;use internally to represent the company I work for: National OPtronics) ; ;This code borrows heavily from parts of the resulting assembler code ;obtained from compiling the WINAVR port of the code that comes loaded ;on the Butterfly. That code was written for the IAR compiler but was ;ported to WINAVR. Sorry, I don't have a clue right now who ported it. ;This information is readily available on www.avrfreaks.net but I am ;too lazy right now to go find it. ; ;AVR application notes 064 and 065 were also indispensable. ; ; .nolist .include "m169def.inc" .list ; ; .cseg .org 0 ; jmp RESET ; Reset Handler jmp EXT_INT0 ; IRQ0 Handler jmp PC_INT0 ; PCINT0 Handler jmp PC_INT1 ; PCINT0 Handler jmp TIM2_COMP ; Timer2 Compare Handler jmp TIM2_OVF ; Timer2 Overflow Handler jmp TIM1_CAPT ; Timer1 Capture Handler jmp TIM1_COMPA ; Timer1 CompareA Handler jmp TIM1_COMPB ; Timer1 CompareB Handler jmp TIM1_OVF ; Timer1 Overflow Handler jmp TIM0_COMP ; Timer0 Compare Handler jmp TIM0_OVF ; Timer0 Overflow Handler jmp SPI_STC ; SPI Transfer Complete Handler jmp USART_RXC ; USART RX Complete Handler jmp USART_DRE ; USART,UDR Empty Handler jmp USART_TXC ; USART TX Complete Handler jmp USI_STRT ; USI Start Condition Handler jmp USI_OVFL ; USI Overflow Handler jmp ANA_COMP ; Analog Comparator Handler jmp ADC_CC ; ADC Conversion Complete Handler jmp EE_RDY ; EEPROM Ready Handler jmp SPM_RDY ; SPM Ready Handler jmp LCD_SOF ; LCD Start of Frame Handler ; RESET: ldi r16, high(RAMEND) ; Main program start out SPH,r16 ; Set Stack Pointer to top of RAM ldi r16, low(RAMEND) out SPL,r16 ; ; ; NOTE: Even (2,4,6) digits utilize the 4 LSB's (bits 3,2,1,0) of ; LCDDRx ; Odd (3,5,7) digits utilize the 4 MSB's (bits 7,6,5,4) of ; LCDCRx ;display the letter N on digit 2, O on digit 3 ; ldi r17,0x00 ; no segments on in digit 2 ldi r18,0x10 ; turn on segment A in digit 3 or r17,r18 ; combine upper and lower nibbles sts LCDDR0,r17 ldi r17,0x07 ; turn on segments F,H,B in digit 2 ldi r18,0x50 ; turn on segments B,F in digit 3 or r17,r18 ; combine upper and lower nibbles sts LCDDR5,r17 ldi r17,0x05 ; turn on segments E,C in digit 2 ldi r18,0x50 ; turn on segments C,E in digit 3 or r17,r18 ; combine upper and lower nibbles sts LCDDR10,r17 ldi r17,0x08 ; turn on segment M in digit 2 ldi r18,0x10 ; turn on segment D in digit 3 or r17,r18 ; combine upper and lower nibbles sts LCDDR15,r17 ; ;display the letter P on digit 4 ; ldi r17,0x01 ; turn on segment A sts LCDDR1,r17 ldi r17,0x05 ; turn on segments B and F sts LCDDR6,r17 ldi r17,0x0E ; turn on segments E, G and L sts LCDDR11,r17 ldi r17,0x00 ; no segments on here sts LCDDR16,r17 call LCD_INIT ; turn on display Loop: rcall Loop ; wait forever ;************************************************************************ LCD_INIT: ;------------------------------------------------------------------------ ; Use external 32 kHz crystal oscillator ; (Note: EXCLK bit of ASSR register needs to be '0' to use 32KHz external ; oscillator, no need to worry about this though as this register is all ; zeroes after reset) ; Setup for 1/3 Bias (LCD2B = 0) ; Setup for 1/4 duty and enable all COM (LCDMUX1,LCDMUX0 = 0b11) pins ; Enable all segment (LCDPM2,LCDPM1,LCDPM0 = 0b111) pins ; ldi r16, (1<<LCDCS) | (0<<LCD2B) | (3<<LCDMUX0) | (7<<LCDPM0) sts LCDCRB, r16 ;------------------------------------------------------------------------ ; ; Dividing LCD clock (32,768HZ) by 16 (LCDPS2,LCDPS1,LCDPS0 = 0b000) ; and dividing output from prescaler by 8 (LCDCD2,LCDCD1,LCDCD0 = 0b111) ; gives a frame rate of 32 Hz ; ldi r16, (0<<LCDPS0) | (7<<LCDCD0) sts LCDFRR, r16 ;------------------------------------------------------------------------ ; Set output voltage to 3.0 V ; ldi r16, (1<<LCDCC3) sts LCDCCR, r16 ;------------------------------------------------------------------------ ; Enable LCD, default waveform and no interrupt enabled ; ldi r16, (1<<LCDEN) sts LCDCRA, r16 ret ;------------------------------------------------------------------------ ;************************************************************************ ; EXT_INT0: reti ; PC_INT0: reti ; PC_INT1: reti ; TIM2_COMP: reti ; TIM2_OVF: reti ; TIM1_CAPT: reti ; TIM1_COMPA: reti ; TIM1_COMPB: reti ; TIM1_OVF: reti ; TIM0_COMP: reti ; TIM0_OVF: reti ; SPI_STC: reti ; USART_RXC: reti ; USART_DRE: reti ; USART_TXC: reti ; USI_STRT: reti ; USI_OVFL: reti ; ANA_COMP: reti ; ADC_CC: reti ; EE_RDY: reti ; SPM_RDY: reti ; LCD_SOF: reti |