Butterfly to JTAG ICE Clone

The Butterfly JTAG ICE Patch by Julie Porter.

Instructions how to convert a Butterfly into a JTAG ICE clone.

Contains object code and a diff file with steps to create sourcecode from the upgrade object code in AVRStudio 4.

NOTE: Original ZIP Archive was Corrupted but has been replaced.

The zip doesn't work pleassssssssssssssssse help? This would be very usefull, Retro.

You are correct. I check the ZIP and it was corrupt. Included is another copy.

This is the JTAG ICE project by Julie Porter.

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Here are some of the issues regarding the Butterfly JTAG ICE clone object code "Patch."

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The sync byte of the ICE is 0x20 or the space character. In the term program, press <space><space> this should return AVRONCDA additional <space> characters will return 'A.'

The tech note AVR060 details the front end. Use Tables 26 and 28 to read some of the parameters (like the voltage) Table 27 gives the responses expected.

The special function segments of the butterfly LCD are used in place of LEDs these will flash when I/O happens. SF segment 1 is used to detect target connection/voltage. It is tied to the inverse of portE6.

During testing it was observed that if the STK dialog was left on the page with the voltage setting, Sometimes studio tries to up the baud rate to the highest setting. A message in the window says that the ICE lost sync; and to power cycle the pod. The work around is to change the page to the advanced or program tab before cycling the power. This could probably be fixed by calibrating the osccal to the baud rate.

The voltage returned is a port to asm from the example application. See below for details, it is affected by the LDR. The c version uses fixed point. The asm port is not working as well as would be desired.

Notes and enhancements.

The original HW used port C to return the hardware revision in the lower for bits. These are anded with either 8 or C to form the returned value. Since the Butterfly does not have a port C free, a fixed return of 0xBF (for butterfly) is returned. Some ICE clones pull Bit 3 high for a return of C1.

Level shifting.

If the ICE-Butterfly is to be used with something like a mega128 that is running at 5v, then level shifting and load balancing is needed. See the plans for the BootICE clones for suggestions as to how to do this. The butterfly must be used with 3.5 or so volts to prevent damage to the Dataflash chip, The ADC is also referenced at 3.x volts through the LDR. Removal of the Dataflash and a replacement of the LDR with a fixed voltage divider can be used if 5V operation is needed.

The main change to the code, other than offsets is the ADC return section. This involved quite a bit of change in that it is necessary to use the LDR to calibrate the vref target (see butterfly sample code.) So the sample takes twice as long, counting to 16. Eight steps for the ADC and 8 steps for the vref.

There are undocumented codes. One of these uses a soft function address pointer to change the PML behavior. These codes have not been tested.

Should ATMEL update the JTAG firmware, it will be necessary to re-locate the JXXXX addresses in the jump table. Changes to SRAM offsets are also a possibility.

Most of the TAP code was left uncommented. This is the IP of the system. Most of the functionality is documented in the 169 datasheets for the programming side. Only places where the code needed patching were notes inserted into the comments field. These were mostly for debugging and searching for mask bits that were held in register constants.

If the code is recompiled, port B be can be used for the TAP port out. That way the JTAG is available to update the board. When using port b in the default configuration; pin 5 is connected to the speaker. This will cause clicks, whistles and screams as the TAP port is accessed. An option is to move the TDI signal to another unused pin.

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The voltage levels are the main reason I recommend Butterfly to butterfly use. I do not have any other JTAG capable chips that are not Debugwire. Since I have not tested the patch with other than a butterfly the best I can offer is use at own risk.

If you look at the clone schematics, most of the hardware in the original was for the voltage conversion. That must be there for a reason, although a lot of DIY plans leave this out.

The caution regarding voltage is based on the advice of Smiley and the rants of Dan. Other parts of the advice regarding voltage levels are rephrasing of cautions from the manual. (And we know how often this group reads the manual or instructions. )

The other stuff, is that the BF Ice clone is not quite plug and play since connections must be made to 3 headers. This means the user has to have an understating of how things work before blindly connecting boards together. Ideally it would be a ribbon cable from JTAG TAP port to JTAG TAP port. This is complexed that reset and the target ref voltage need to connect to other headers.

- Julie Porter

TThank you!! Especially JPorter for this....now I can tet how a JTAG works!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

You are very welcome!

Don't forget to report back and let us know how you made out and what you thought of this package.